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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a AD1954 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?analog devices, inc., 2002 sigmadsp 3-channel, 26-bit signal processing dac functional block diagram features 5 v 3-channel audio dac system accepts sample rates up to 48 khz seven biquad filter sections per channel dual dynamic processor with arbitrary input/output curve and adjustable time constants 0 ms to 6 ms variable delay/channel for speaker alignment stereo spreading algorithm for phat stereo effect program ram allows complete new program download via spi port parameter ram allows complete control of more than 200 parameters via spi port spi port features safe-upload mode for transparent filter updates two control registers allow complete control of modes and memory transfers differential output for optimum performance 112 db signal-to-noise (not muted) at 48 khz sample rate (a-weighted stereo) 70 db stop-band attenuation on-chip clickless volume control hardware and software controllable clickless mute digital de-emphasis processing for 32 khz, 44.1 khz, and 48 kh z sample rates flexible serial data port with right-justified, left-justified, i 2 s-compatible, and dsp serial port modes auxiliary digital input product overview the AD1954 is a complete 26-bit single-chip 3-channel digital audio playback system with built-in dsp functionality for speaker equalization, dual-band compression/limiting, delay compensa- tion, and image enhancement. these algorithms can be used to compensate for real-world limitations of speakers, amplifiers, and listening environments, resulting in a dramatic improvement of perceived audio quality. the signal processing used in the AD1954 is comparable to that found in high-end studio equipment. most of the processing is done in full 48-bit double-precision mode, resulting in very good low-level signal performance and the absence of limit cycles or idle tones. the compressor/limiter uses a sophisticated two-band algorithm often found in high end broadcast compressors. (continued on page 9) graphical custom programming tools 44-lead mqfp or 48-lead lqfp plastic p ackage applications 2.0/2.1 channel audio systems (two main channels plus subwoofer) multimedia audio automotive sound systems minicomponent stereo home theater systems (ac-3 post processor) musical instruments in-seat sound systems (aircraft, motor coaches) serial control interface mclk mux mclk generator ( 256f s / 512f s ) dac ?l dac ?r dac sw digital out a udio data mux 26 22 dsp core data f ormat: 3.23 (single precision) 3.45 (double precision) ram rom 3 3 3 3 3 analog outputs AD1954 master clock output serial data inputs master clock inputs serial data output spi input spi data output au x serial data input digital output sigmadsp and phat stereo are trademarks of analog devices, inc.
rev. 0 AD1954 ? table of contents features/applications/product overview . . 1 functional block diagram . . . . . . . . . . . . . . . . . 1 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 absolute maximum ratings . . . . . . . . . . . . . . . . . 6 ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 pin configurations . . . . . . . . . . . . . . . . . . . . . . . . . . 6 pin function descriptions . . . . . . . . . . . . . . . . . . 7 typical performance characteristics . . . . . 8 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 signal processing . . . . . . . . . . . . . . . . . . . . . . . . . . 12 signal processing overview . . . . . . . . . . . . . . . . . . . . . . . 12 numeric formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 high-pass filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 biquad filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 stereo image expander . . . . . . . . . . . . . . . . . . . . . . . . . . 14 delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 main compressor/limiter . . . . . . . . . . . . . . . . . . . . . . . . 15 subwoofer compressor/limiter . . . . . . . . . . . . . . . . . . . . 17 de-emphasis filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 using the sub reinjection paths for systems with no subwoofer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 interpolation filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 spi port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 spi address decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 volume registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 parameter ram contents . . . . . . . . . . . . . . . . . . . . . . . . 22 options for parameter updates . . . . . . . . . . . . . . . . . . . . 24 soft shutdown mechanism . . . . . . . . . . . . . . . . . . . . . . 24 safeload mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 summary of ram modes . . . . . . . . . . . . . . . . . . . . . . . 24 parameter ram read/write format (single address) . . 25 parameter ram block read/write format (burst mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 program ram read/write format (single address) . . . . 25 program ram block read/write format (burst mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 spi control register 1 write format . . . . . . . . . . . . . . . 25 spi control register 1 read format . . . . . . . . . . . . . . . . 25 spi control register 2 write format . . . . . . . . . . . . . . . 25 spi volume register write format . . . . . . . . . . . . . . . . . 25 data capture register write format . . . . . . . . . . . . . . . . 26 data capture serial out register (address and register select) write format . . . . . . . . . . 26 data capture read format . . . . . . . . . . . . . . . . . . . . . . . 26 safeload register write format . . . . . . . . . . . . . . . . . . . . 26 spi read/write data formats . . . . . . . . . . . . . . . 26 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 setting the clock mode . . . . . . . . . . . . . . . . . . . . . . . . . . 26 setting the data and mclk input selectors . . . . . . . . . . 27 data capture registers . . . . . . . . . . . . . . . . . . . . 27 serial data input port . . . . . . . . . . . . . . . . . . . . . 29 serial data input modes . . . . . . . . . . . . . . . . . . . . . . . . . 29 digital control pins . . . . . . . . . . . . . . . . . . . . . . . 30 mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 de-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 analog output section . . . . . . . . . . . . . . . . . . . . 30 graphical custom programming tools . . . . 31 appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . 33
rev. 0 ? rev. 0 AD1954?pecifications test conditions, unless otherwise noted. supply voltages (av dd , dv dd ) . . . . . . . . . . . . . . . . . . . 5.0 v ambient temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 25 c input clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.288 mhz input signal . . . . . . . . . . . . . . . . . . 1.000 khz 0 db full scale input sample rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 khz measurement bandwidth . . . . . . . . . . . . . . . 20 hz to 20 khz word width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 bits load capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . 2200 pf load impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.74 k ? input voltage high . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0 v input voltage low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8 v analog performance* parameter min typ max unit resolution 24 bits signal-to-noise ratio (20 hz to 20 khz) (left/right output) no filter (stereo) 109 db with a-weighted filter 112 db dynamic range (20 hz to 20 khz, ?0 db input) (left/right output) no filter 109 db with a-weighted filter 109 112 db total harmonic distortion plus noise (left/right output) v o = ?.5 db ?3 ?00 db signal-to-noise ratio (20 hz to 20 khz) (subwoofer output) no filter (stereo) 104 db with a-weighted filter 107 db dynamic range (20 hz to 20 khz, ?0 db input) (subwoofer output) no filter 104 db with a-weighted filter 104 107 db total harmonic distortion plus noise (subwoofer output) v o = ?.5 db ?0 ?6 db analog outputs differential output range ( full scale) (left/right output) 2.74 v p-p differential output range ( full scale) (subwoofer output) 2.77 v p-p cmout 2.50 v dc accuracy gain error (left/right channel) ? +5 % gain error (subwoofer channel) ? +8 % interchannel gain mismatch ?.250 +0.250 db gain drift 150 ppm/ c dc offset ?0 +30 mv interchannel crosstalk (eiaj method) ?20 db interchannel phase deviation 0.1 degrees mute attenuation ?07 db de-emphasis gain error 0.1 db * performance of right and left channels are identical (exclusive of the interchannel gain mismatch and interchannel phase deviat ion specifications). specifications subject to change without notice.
rev. 0 AD1954 ? digital i/o parameter min typ max unit input voltage high (v ih ) 2.1 v input voltage high (v ih ) ?resetb 2.25 v input voltage low (v il ) 0.8 v input leakage (i ih @ v ih = 2.1 v) 10 a input leakage (i il @ v il = 0.8 v) 10 a high level output voltage (v oh ), i oh = 2 ma dvdd ?0.5 v low level output voltage (v ol ), i ol = 2 ma 0.4 v input capacitance 20 pf specifications subject to change without notice. power parameter min typ max unit supplies * voltage, analog and digital 4.5 5 5.5 v analog current 42 48 ma analog current, power-down 40 46 ma digital current 60 67 ma digital current, spi power-down 6 10 ma digital current, reset power-down 51 59 ma dissipation operation, both supplies 510 mw operation, analog supplies 210 mw operation, digital supplies 300 mw spi power-down, both supplies 230 mw reset power-down, both supplies 455 mw power supply rejection ratio 1 khz 300 mv p-p signal at analog supply pins ?0 db 20 khz 300 mv p-p signal at analog supply pins ?0 db * odvdd current is dependent on load capacitance and clock rate. specifications subject to change without notice. temperature range parameter min typ max unit specifications guaranteed 25 c functionality guaranteed ?0 105 c storage ?5 125 c specifications subject to change without notice.
rev. 0 ? AD1954 digital filter characteristics at 44.1 khz parameter min typ max unit pass-band ripple 0.01 db stop-band attenuation 70 db pass band 20 khz 0.5442 f s stop band 24 khz 0.4535 f s group delay 24.625/f s sec specifications subject to change without notice. digital timing parameter min typ max unit t dmp mclk period (512 f s mode) 41 ns t dmp mclk period (256 f s mode) 81 ns t dmd mclk recommended duty cycle @ 12.288 mhz (256 f s mode) 45 55 % t dmd mclk recommended duty cycle @ 24.576 mhz (512 f s mode) 40 60 % t dmd mclk delay (all mode) 25 ns t dbh bclk low pulsewidth 10 ns t dbh bclk high pulsewidth 10 ns t dbd bclk delay (to bclko) 25 ns t dls lrclk setup 0 ns t dlh lrclk hold 10 ns t dld lrclk delay (to lrclko) 25 ns t dds sdata setup 0 ns t ddh sdata hold 10 ns t ddd sdata delay (to sdatao) 25 ns t ccl cclk low pulsewidth 12 ns t cch cclk high pulsewidth 12 ns t cls clatch setup 10 ns t clh clatch hold 10 ns t cld clatch high pulsewidth 10 ns t cds cdata setup 0 ns t cdh cdata hold 10 ns t cod cout delay 35 ns t coh cout hold 2 ns t dcd dcsout delay 35 ns t dch dcsout hold 2 ns t pdrp pd/rst low pulsewidth 5 ns specifications subject to change without notice.
rev. 0 AD1954 ? caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD1954 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device 44-lead mqfp 48-lead lqfp 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 39 38 37 43 42 41 40 pin 1 identifier top view (not to scale) nc agnd voutl voutl+ avdd agnd avdd nc mclk2 mclk1 mclk0 deemp/sdata_aux mute dvdd nc = no connect sdata2 bclk2 lrclk2 sdata1 voutr+ voutr agnd vouts+ AD1954 bclk1 vouts dgnd mclkout cout dcsout odvdd lrclkout bclkout sdataout zeroflag filtercap vref nc dgnd lrclk1 sdata0 bclk0 lrclk0 cdata cclk clatch resetb avdd agnd nc 3 4 5 6 7 1 2 10 11 8 9 40 39 38 41 42 43 44 36 35 34 37 29 30 31 32 33 27 28 25 26 23 24 pin 1 identifier top view (not to scale) 12 13 14 15 16 17 18 19 20 21 22 resetb avdd agnd agnd voutl voutl+ avdd agnd avdd voutr+ AD1954 cdata lrclk1 sdata0 bclk0 lrckl0 cclk mclk2 mclk1 mclk0 deemp/sdata_aux mute dvdd sdata2 bclk2 lrclk2 sdata1 bclk1 voutr agnd vouts+ vouts clatch dgnd cout odvdd bclkout mclkout dcsout lrclkout sdataout zeroflag filtcap vref dgnd absolute maximum ratings * dvdd to dgnd . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +6 v odvdd to dgnd . . . . . . . . . . . . . . . . . . . . . ?.3 v to +6 v avdd to agnd6 . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +6 v digital inputs . . . . . . . . . . dgnd ?0.3 v to dvdd + 0.3 v analog inputs . . . . . . . . . . agnd ?0.3 v to avdd + 0.3 v agnd to dgnd . . . . . . . . . . . . . . . . . . . . ?.3 v to + 0.3 v reference voltage . . . . . . . . . . . . . . . . . . . (avdd + 0.3)/2 v maximum junction temperature . . . . . . . . . . . . . . . . 125 c storage temperature range . . . . . . . . . . . . ?5 c to +150 c soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 c/10 sec * stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. ordering guide model temperature range package description package option AD1954ys ?0 c to +105 c 44-lead mqfp s-44 AD1954ysrl ?0 c to +105 c 44-lead mqfp s-44 on 13" reel AD1954yst ?0 c to +105 c 48-lead lqfp st-48 AD1954ystrl 40 c to +105 c 48-lead lqfp st-48 on 13" reel package characteristics (44-lead mqfp) min typ max unit ja (thermal resistance [junction to ambient]) 72 c/w jc (thermal resistance [junction to case]) 19.5 c/w package characteristics (48-lead lqfp) min typ max unit ja (thermal resistance [junction to ambient]) 76 c/w jc (thermal resistance [junction to case]) 17 c/w pin configurations
rev. 0 AD1954 ? pin function descriptions pin no. pin no. input/ (44-mqfp) (48-lqfp) mnemonic output description 1n cn o connect 12 mclk2 in master clock input 2 256 f s /512 f s 23 mclk1 in master clock input 1 256 f s /512 f s 34 mclk0 in master clock input 0 256 f s /512 f s 45 deemp/ in enables 44.1 khz de-emphasis filter (others available through spi control)/ sdata_aux auxiliary serial data input 56 mute in mute signal. initiates volume ramp-down. 67 dvdd digital supply for dsp core, 4.5 v?.5 v 78s data2 in serial data input 2 89 bclk2 in bit clock 2 91 0 lrclk2 in left/right clock 2 10 11 sdata1 in serial data input 1 11 12 bclk1 in bit clock 1 12 13 dgnd digital ground 13 14 lrclk1 in left/right clock 1 14 15 sdata0 in serial data input 0 15 16 bclk0 in bit clock 0 16 17 lrclk0 in left/right clock 0 17 18 cdata in spi data input 18 19 cclk in spi data bit clock 19 20 clatch in spi data framing signal 20 21 resetb in reset signal, active low 21 22 avdd analog 5 v supply 22 23 agnd analog gnd 24 nc no connect 23 25 vouts out negative subanalog dac output 24 26 vouts+ out positive subanalog dac output 25 27 agnd analog gnd 26 28 voutr out negative left analog dac output 27 29 voutr+ out positive left analog dac output 28 30 avdd analog 5 v supply 29 31 agnd analog gnd 30 32 avdd analog 5 v supply 31 33 voutl+ out positive left analog dac output 32 34 voutl out negative left analog dac output 33 35 agnd analog gnd 36 nc no connect 37 nc no connect 34 38 vref in connection for filtered avdd/2 35 39 filtcap in connection for noise reduction capacitor 36 40 zeroflag out zero flag output. high when both left and right channels are 0 for 1024 frames. 37 41 sdataout out serial data mux output 38 42 bclkout out bit clock mux output 39 43 lrclkout out left/right clock mux output 40 44 odvdd digital supply pin for output drivers, 2.5 v?.5 v 41 45 dcsout out data capture serial output for data capture registers. use in conjunction with selected lrclk and bclk to form a 3-wire output. 42 46 cout out spi data output. tri-stated when inactive. 43 47 mclkout out master clock output 512 f s /256 f s (frequency selected by spi register) 44 48 dgnd digital ground
AD1954?ypical performance characteristics ? rev. 0 performance plots the following plots demonstrate the performance achieved on the actual silicon. tpc 1 shows a fft of a full-scale 1 khz signal, with a thd+n of ?00 db, which is dominated by a second harmonic. tpc 2 shows a fft of a ?0 db sine wave, demonstrating the lack of low-level artifacts. tpc 3 shows a frequency response plot with the seven equalization biquads set to an alternating pattern of 6 db boosts and cuts. tpc 4 shows a linearity plot, where the measurement was taken with the same equalization curve used to make tpc 3. when the biquad filters are not in use, the signal passes through the filters with no quantization effects. tpc 4 therefore demonstrates that using double-precision math in the biquad filters has virtually eliminated any quantization artifacts. tpc 5 shows a tone-burst applied to the compressor, with the attack and recovery characteristics plainly visible. the rms detector was programmed for normal rms time constants; the hold/decay feature was not used for this plot. 0 ?60 020 2468 14 16 18 ?0 ?0 ?20 ?0 ?0 ?00 ?40 10 12 khz db tpc 1. fft of full-scale sine wave (32 k ? points) 0 ?60 020 2468 141618 ?0 ?0 ?20 ?0 ?0 ?00 ?40 10 12 khz db tpc 2. fft of ?0 db sine wave (32 k ? points) hz 0 ?0 20 10k ?0 1k 100 ? ? ? ? ?2 ?4 ?6 ?8 50 200 500 5k db 2k tpc 3. frequency response of eq biquad filters 3.0 ?.0 ?20 0 ?00 ?0 ?0 0.5 ?.0 ?.0 0 ?.5 ?.5 ?.5 ?0 ?0 dbfs 2.5 1.5 2.0 1.0 db tpc 4. linearity plot ?.0 ?20 0 ?00 ?0 ?0 ?0 ms ?.5 ?.0 ?.5 0 0.5 1.0 1.5 2.0 v tpc 5. tone-burst response with compressor threshold set to ?0 db
rev. 0 AD1954 ? product overview (continued from page 1) an extensive spi port allows click-free parameter updates, along with read-back capability from any point in the algorithm flow. the AD1954 includes adi? patented multibit sigma-delta dac architecture. this architecture provides 112 db snr and dynamic range and thd+n of ?00 db. these specifications allow the AD1954 to be used in applications ranging from low end boom boxes to high end professional mixing/editing systems. the AD1954 also has a digital output that allows it to be used purely as a dsp. this digital output can also be used to drive an external dac to extend the number of channels beyond the three that are provided on the chip. this chip can be used with either its default signal processing program or with a custom user-designed program. graphical pro- gramming tools are available from adi for custom programming. f eatures t he AD1954 is comprised of a 26-bit dsp (48 bit with double precision) for interpolation and audio processing, three multibit sigma-delta modulators, and analog output drive circuitry. other features include an on-chip parameter ram that uses a safe- upload feature for transparent and simultaneous updates of filter coefficients and digital de-emphasis filters. also, on-chip i nput selectors allow up to three sources of serial da ta a nd ma s ter clock to be selected. the 3-channel configu- ration is especially u seful for 2.1 playback systems that include two satellite speak ers and a subwoofer. the default program allows for independent equalization and compression/limiting for the satellite and subwoofer outputs. f igure 1 shows the block diagram of the device. the AD1954 contains a program ram that boots from an internal program rom on power-up. signal-processing parameters are stored in a 256-location parameter ram that is initialized on power-up by an internal boot rom. new values are written to the parameter ram using the spi port. the values stored in the parameter ram control the iir equalization filters, the dual- band compressor/limiter, the delay values, and the settings of the stereo spreading algorithm. the AD1954 has a very sophisticated spi port that supports complete read/write capability of both the program and the parameter ram. two control registers are also provided to control the chip serial modes and various other optional features. hand- shaking is also included for ease of memory uploads/downloads. the AD1954 contains four independent data capture circuits that can be programmed to tap the signal flow of the processor at any point in the dsp algorithm flow. these captured signals can be accessed either through a separate serial out pin (i.e., that can be connected to an external dac or dsp) or by reading from the data capture spi registers. this allows the basic functional ity of the AD1954 to be easily extended. the processor core in the AD1954 has been designed from the ground up for straightforward coding of sophisticated compression/ limiting algorithms. the AD1954 contains two independent compressor/limiters with rms-based amplitude detection and attack/hold/release controls, together with an arbitrary compression curve that is loaded by the user into a look-up table that resides in the parameter ram. the compressor also features look-ahead compression that prevents compressor overshoots. 3:1 a udio data mux 1 3 3 spi port 3:1 mclk mux 1 dac ?l coefficient rom 64 22 26 22 dsp core data f ormat: 3.23 (single precision) 3.45 (double precision) 3 3 analog outputs master clock i/o group dcsout spi i/o group 3 serial in 1 da ta memory, 512 26 control registers trap reg. (i 2 s, spi) safeload registers program ram 512 35 p arameter ram 256 22 boot rom boot rom memory controllers dac ?r dac sw 2 bias analog bias group resetb mute de-emphasis zeroflag notes 1 controlled through spi control registers. 2 dac does not use digital interpolation. serial data i/o group dcsout trap au x serial data input mclk generator 1 (256 f s /512 f s in) 256 f s /512 f s out vo ltag e reference vref dvdd av dd odvdd 3 filtcap a gnd dgnd 32 figure 1. block diagram
rev. 0 AD1954 ?0 the AD1954 has a very flexible serial data input port that allows for glueless interconnection to a variety of adcs, dsp chips, aes/ebu receivers, and sample rate converters. the AD1954 can be configured in left-justified, i 2 s, right-justified, or dsp serial port compatible modes. it can support 16 bits, 20 bits, and 24 bits in all modes. the AD1954 accepts serial audio data in msb first, two? complement format. the part can also be set up in a 4-channel serial input mode by simultaneously using the serial input mux and the auxiliary serial input. the AD1954 operates from a single 5 v power supply. it is fabricated on a single monolithic integrated circuit and is housed in a 44-lead mqfp or 48-lead lqfp package for operation over the temperature range ?0 c to +105 c. pin functions all input pins have a logic threshold compatible with ttl input levels and may therefore be used in systems with 3.3 v logic. all digital output levels are controlled by the odvdd pin, which may range from 2.7 v to 5.5 v, for compatibility with a wide range of external devices. (see pin function descriptions.) sdata0, sdata1, sdata2 ?erial data inputs. one of these three inputs is selected by an internal mux, set by writing to bits 7 and 6 in control register 2. default is 00, which selects sdata0. the serial format is selected by writing to bits 3? of control register 0. see spi read/write data formats section for recommendations on how to change input sources without causing a click or pop noise. lrclk0, lrclk1, lrclk2 ?eft/right clocks for framing the input data. the active lrclk input is selected by writing to bits 7 and 6 in control register 2. the default is 00, which se lects lrclk0. the interpretation of the lrclk changes according to the serial mode, set by writing to control register 0. bclk0, bclk1, bclk2 ?erial bit clocks for clocking in the serial data. the active bclk input is selected by writing to bits 7 and 6 in control register 2. default is 00, which selects bclk0. the interpretation of bclk changes according to the serial mode, which is set by writing to control register 0. lrclkout, bclkout, sdataout output of mux that selects one of the three serial input groups. these pins may be used to send the selected serial input signals to other external devices. this output pin is enabled by writing a 1 to bit 8 of control register 2. the default mode is 0 or off. mclk0, mclk1, mclk2 ?aster clock inputs. active input selected by writing to b its 5 and 4 of control register 2. t he default is 00, which selects mclk0. the master clock frequency must be either 256 f s or 512 f s , where f s is the input sampling rate. the master clock fre quency is programmed by writing to bit 2 of control register 2. the default is 0 (512 f s ). see initialization section for rec ommen- da tions concerning how to change clock sources without causing an audio click or pop. note that since the de fault mclk source pin is mclk0, there must be a clock signal present on this pin on power-up so that the AD1954 can comp lete its initialization routine. mclkout ?aster clock output. the master clock output pin may be programmed to produce either 256 f s , 512 f s , or a copy of the selected mclk input pin. this pin is programmed by writing to bits 1 and 0 of control register 2. the default is 00, which disables the mclko pin. cdata ?erial data in for the spi control port. see spi port section for more information on spi port timing. cout ?erial data output. this is used for reading back registers and memory locations. it is tri-stated when an spi read is not active. see spi port section for more information on spi port timing. cclk ?pi bit rate clock. this pin either may run continuously or be gated off in between spi transactions. see spi port section for more information on spi port timing. clatch ?pi latch signal. it must go low at the beginning of an spi transaction and high at the end of a transaction. each spi transaction may take a different number of cclks to complete, depending on the address and read/write bit that are sent at the beginning of the spi transac tion. detailed spi timing information is given in spi port section. resetb ?ctive-low reset signal. after resetb goes high, the AD1954 goes through an initial ization sequence where the program and parameter rams are initial ized with the contents of the on-board boot roms. all spi registers are set to 0, and the data rams are also zeroed. the initializa- tion is complete after 1024 mclk cycles. since the mclk in freq select (bit 2 in control register 2) defaults to 512 f s at power-up, this initialization will proceed at the exter nal mclk rate and will take 1024 mclk cycles to complete, regardless of the absolute frequency of the external mclk. new values sh ould not be written to the spi port until the initialization is complete. zeroflag ?ero-input indicator. this pin will go high if both serial inputs have been inactive (zero data) for 1024 lrclk cycles. this pin may be used to drive an external mute fet for reduced noise during digital silence. this pin also functions as a test out pin, controlled by the test register at spi address 511. while most test modes are not useful to the end user, one may be of some use. if the test reg ister is programmed with the number 7 (decimal), the zeroflag output will be switched to the output of the internal pseudo-random noise generator. this noise generator operates at a bit rate of 128 f s and has a repeat time of once per 2 24 cycles. this mode may be used to generate white noise (or, with appropri- ate filtering, pink noise) to be used as a test signal for measuring speakers or room acoustics. dcsout ?ata capture serial out. this pin will output the dsp? internal signals, which can be used by external dacs or other signal-processing devices. the signals that are captured and output on the dcsout pin are controlled by writing program counter trap numbers to spi addresses 263 (for the left output) and 264 (for the right out- put). when the internal program counter contents are equal to the trap values written to the spi port, the selected dsp register is transferred to the dcsout parallel-to-serial registers and shifted out on the dcsout pin. table xx shows the program counter trap values and register-select values that should be used to tap various internal points of the algorithm flow.
rev. 0 AD1954 ?1 the dcsout pin is meant to be used in conjunction with the lrclk and bclk signals that are provided to the serial input port. the format of dcsout is the same as the format used for the serial port. in other words, if the serial port is running in i 2 s mode, then the dcsout pin, together with the lrclk0 and bclk0 pins (assuming input 0 is selected), will form a valid 3-wire i 2 s output. the dcsout pin can be used for a variety of purposes. if the dcsout pin is used to drive another external dac, then a 4.1 system is possible using a new program downloaded into the program ram. deemp/sdata_aux ?e-emphasis input pin/auxiliary serial data input. in de-emphasis mode, if this pin is asserted high, then a digital de-emphasis filter will be inserted into the signal flow. the de-emphasis curve is valid only for a sample rate of 44.1 khz; curves for 32 khz and 48 khz may be programmed using the spi port. this pin can also be used as an auxiliary 2-channel serial data input. this function is set by writing a ??to bit 11 of control register 1. the same clocks are used for this serial input as are used for the sdata0, sdata1, and sdata2 signals. this serial input can only be used in the signal process ing flow when using analog devices custom programming tools (see page 31). the use of de-emphasis is still avail able while this pin is used as a serial input but only through spi control. mute ?ute output signal. when this pin is asserted high, a ramp sequence is started that gradually reduces the volume to zero. when de-asserted, the volume ramps from zero back to the original volume setting. the ramp speed is timed so that it takes 10 ms to reach zero volume when starting from the default 0 db volume setting. voutl+, voutl ? eft-channel differential analog outputs. full-scale outputs correspond to 1 v rms on each output pin or 2 v rms differential, assuming a vref input voltage of 2.5 v. the full-scale swing scales directly with vref. these outputs are capable of driving a load of >5 k ? , with a maximum peak current of 1 ma from each pin. an external third order filter is recommended for filtering out-of-band noise. voutr+, voutr ?ight channel differential outputs. output characteristics are the same as for voutl+, voutl?above. vouts+, vouts ?ubchannel differential outputs. these outputs are designed to drive loads of 10 k ? or greater, with a peak current capability of 250 a. this output does not use digital interpolation, since it is intended for low-frequency application. an external third order filter with a cutoff frequen cy <2 khz is recommended. vref ?nalog reference voltage input. the nominal vref input voltage is 2.5 v; the analog gain scales directly with the voltage on this pin. when using the AD1954 to drive a power amplifier, it is recommended that the vref voltage be derived by dividing down and heavily filtering the supply to the power amplifier. this provides a benefit if the compressor/limiter in the AD1954 is used to prevent amplifier clipping. in this case, if the dac output voltage is scaled to the amplifier power supply, a fixed compressor threshold can be used to protect an amplifier whose supply may vary over a wide range. any ac signal on this pin will cause distortion, and therefore, a large decoupling capacitor may be necessary to ensure that the voltage on vref is clean. the input impedance of vref is greater than 1 m ? . filtcap ?ilter capacitor point. this pin is used to reduce the noise on an internal biasing point, in order to provide the highest performance. it may not be necessary to connect this pin, depending on the quality of the layout and the grounding used in the application circuit. dvdd ?igital vdd for core. 5 v nominal. odvdd ?igital vdd for all digital outputs. variable from 2.7 v to 5.5 v.
rev. 0 AD1954 ?2 numeric formats it is common in dsp systems to use a standardized method of specifying numeric formats. to better comprehend issues relating to precision and overflow, it is helpful to think in terms of frac- tional two? complement number systems. fractional number systems are specified by an a.b format, where a is the number of bits to the left of the decimal point, and b is the number of bits to the right of the decimal point. in a two? complement system, there is also an implied offset of one-half of the binary range; for example, in a two? complement 1.23 system, the legal signal range is ?.0 to +(1.0 ?1 lsb). the AD1954 uses two different numeric formats: one for the coefficient values (stored in the parameter ram) and one for the signal data values. the coefficient format is as follows: coefficient format coefficient format: 2.20 range: ?.0 to +(2.0 ?1 lsb) examples: 1000000000000000000000 = ?.0 1100000000000000000000 = ?.0 1111111111111111111111 = (1 lsb below 0.0) 0000000000000000000000 = 0.0 0100000000000000000000 = 1.0 0111111111111111111111 = (2.0 ?1 lsb) this format is used because standard biquad filters require coefficients that range between +2.0 and ?.0. it also allows gain to be inserted at various places in the signal path. internal dsp signal data format input data format: 1.23 this is sign extended when written to the data memory of the AD1954. internal dsp signal data format: 3.23 range: ?.0 to +(4.0 ?1 lsb) examples: 10000000000000000000000000 = ?.0 11000000000000000000000000 = ?.0 11100000000000000000000000 = ?.0 11111111111111111111111111 = (1 lsb below 0.0) 00000000000000000000000000 = 0.0 00100000000000000000000000 = 1.0 01000000000000000000000000 = 2.0 01111111111111111111111111 = (4.0 ?1 lsb). dgnd (2) ?igital ground. avdd (3) ?nalog vdd. 5 v nominal. for best results, use a separate regulator for avdd. bypass capacitors should be placed close to the pins and connected directly to the analog ground plane. agnd (3) ?nalog ground. for best performance, separate nonoverlapping analog and digital ground planes should be used. signal processing signal processing overview figure 2 shows the signal processing flow diagram of the AD1954. the AD1954 is designed to provide all the signal processing functions commonly used in 2.0 or 2.1 playback systems. a seven-biquad equalizer operates on the stereo input signal. the output of this equalizer is fed to a two- biquad crossover filter for the main channels, and the mono sum of the left and right equalizer outputs is fed to a three- biquad crossover filter for the subchannel. each of the three channels has independent delay compensation. there are two high-quality compressor/limiters available: one operating on the left/right outputs and one operating on the subwoofer channel. the subwoofer output may be blended back into the left/right outputs for 2.0 playback systems. in this configura- tion, the two independent compressor/limiters provide two-band compression, which significantly improves the sound quality of compressed audio. in addition, the main channels have a stereo widening algorithm that increases the perceived spread of the stereo image. most of the signal processing functions are coded using full 48- bit double-precision arithmetic. the input word length is 24 bits, with two extra headroom bits added in the processor to allow internal gains up to 12 db without clipping (additional gains can be accommodated by scaling down the input signal in the first biquad filter section). a graphical user interface (gui) is available for evaluation of the AD1954 (figure 3). this gui controls all of the functions of the chip in a very straightforward and user-friendly interface. no code needs to be written to use the gui to control the chip. for more information on AD1954 software tools, send an e-mail to sigmadsp@analog.com. each section of this flow diagram will be explained in detail on the following pages. hpf/ deemph hpf/ deemph in right in left volume volume phat stereo delay (0 ms?.7ms) delay (0 ms?.7ms) delay (0 ms?.3ms) delay (0 ms?.3ms) 8 interpolation dac out left 8 interpolation dac out right volume 1 biquad filter delay (0 ms?.7ms) mono dac l/r reinjection level subwoofer output sub dynamics processor sub channel l/r mix eq and crossover filters l/r dynamics processor level detect, look-up table level detect, look-up table 7 biquad filters 7 biquad filters crossover (2 filters) crossover (2 filters) crossover (3 filters) figure 2. signal processing flow
rev. 0 AD1954 ?3 the sign extension between the serial port and the dsp core allows for up to 12 db of gain in the signal path without internal clipping. gains greater than 12 db can be accommodated by scaling the input down in the first biquad filter and scaling the signal back up at the end of the biquad filter section. a digital clipper circuit is used between the output of the dsp core and the input to the dac sigma-delta modulators, to prevent overloading the dac circuitry (see figure 4). note that there is a gain factor of 0.75 used in the dac interpolation filters, and therefore signal values of up to 1/0.75 will pass- through the dsp without clipping. since the dac is designed to produce an analog output of 2 v rms (differential) with a 0 db digital input, signals between 0 db and 1/0.75 (approximately 3 db) will produce larger analog outputs and result in slightly degraded analog performance. this extra analog range is neces- sary in order to pass 0 dbfs square waves through the system, since these square waves cause overshoots in the interpolation filters that would otherwise briefly clip the digital dac circuitry. a separate digital clipper circuit is used in the dsp core to ensure that any accumulator values that exceed the numeric 3.23 format range are clipped when taken from the accumulator. high-pass filter the high-pass filter is a first order double-precision design. the purpose of the high-pass filter is to remove digital dc from the input. if this dc were allowed to pass, the detectors used in the figure 3. graphical user interface signal processing (3.23 format) serial port dac interpolation filters (3.23 format) digital sigma-delta modulators (1.23 format) digital clipper data in 2-bit sign extention 0.75 1.23 3.23 figure 4. numeric precision and clipping structure compressor/limiter would give an incorrect reading for low signal levels. the high-pass filter is controlled by a single parameter (alpha_hpf), which is programmed by writing to spi loc a tion 180 in 2.20 two? complement format. the foll owing equation can be used to calculate the parameter alpha_hpf from the ? db point of the filter: alpha hpf exp hpf cutoff f s _. ? _ = ? ? ? ? ? ? 10 20 where exp is the exponential operator, hpf_cutoff is the high- pass cutoff in hz, and f s is the audio sampling rate. the default value for the ? db cutoff of the high-pass filter is 2.75 hz at a sampling rate of 44.1 khz. biquad filters each of the two input channels has seven second order biquad sections in the signal path. in addition, the left and right channels have two additional biquad filters that may be used either as cross- over filters or as additional equalization filters. the sub channel has three additional biquad filters that are also to be used as equaliza tion and/or crossover filters. in a typical scenario, the first seven biquads would be used for speaker equalization and/or tone controls and the remaining filters would be programmed to function as cross over filters. note that there is a common equal- ization section used for both the main and sub channels, followed
rev. 0 AD1954 ?4 by the crossover filters. this arrangement prevents any interaction from occurring betw een the crossover filters and the equalization filters. one section of the biquad iir filter is shown in figure 5. b0 in out b1 b2 a1 a2 z ? z ? z ? z ? figure 5. biquad filter this section implements the transfer function: hz bbz bz az a z () = + + () ? () 01 11 2 12 12 2 the coefficients a1 , a2 , b0 , b1 , and b2 are all in two? comple- ment 2.20 format with a range from ? to +2 (minus 1 lsb). the negative sign on the a1 and a2 coefficients is the result of adding both the feed-forward ??terms as well as the feedback ??terms. some digital filter packages automatically produce the correct a1 and a2 coefficients for the topology of figure 5, while others assume a denominator of the form 1 + a1 z ? + a2 z ? . in this case, it may be necessary to invert the a1 and a2 terms for proper operation. the biquad structure shown in figure 5 is coded using double- precision math to avoid limit cycles from occurring when low frequency filters are used. the coefficients are pro- grammed by writing to the appropriate location in the parameter ram, through the spi port (see table vi). there are two possible scenarios for controlling the biquad filters: 1. dynamic adjustment (e.g., bass/treble control or parametric equalizer). when using dynamic filter adjustment, it is highly recom- mended that the user employ the safeload mechanism to avoid temporary instability when the filters are dynamically updated. this could occur if some, but not all, of the coeffi- cients were updated to new values when the dsp calculates the filter output. the operation of the safeload registers is detailed in the options for parameter updates section. 2. setting static eq curve after power-up. if many of the biquad filters need to be initialized after power- up (e.g., to implement a static speaker correction curve), the recommended procedure is to set the processor shutdown bit, wait for the volume to ramp down (about 20 m s), and then write directly to the parameter ram in burst mode. after the ram is loaded, the shutdown bit can be de-as serted, causing the volume to ramp back up to the initial value. this entire procedure is click-free and faster than using th e safeload mechanism. the data paths of the AD1954 contain an extra two bits on top of the 24 bits that are input to the serial port. this allows up to 12 db of boost without clipping. however, it is important to remember that it is possible to design a filter that has less than 12 db of gain at the final filter output, but more than 12 db of gain at the output of one or more intermediate biquad filter sections. for this reason, it is important to cascade the filter sections in the correct order, putting the sections with the largest peak gains at the end of the chain rather than at the beginning. this is standard practice when coding iir filters and is covered in basic books on dsp coding. if gains larger than 12 db cannot be avoided, then the coeffi- cients b0 through b2 of the first biquad section may be scaled down to fit the signal into the 12 db maximum signal range and then scaled back up at the end of the filter chain. volume three separate spi registers are used to control the volume one each for the left, right, and sub channels. these registers are special in that they include automatic digital ramp circuitry for clickless volume adjustment. the volume control word is in 2.20 format and therefore gains from +2.0 to ?.0 are possible. the default value is 1.0. it takes 1024 audio frames to adjust the volume from 2.0 down to 0; in the normal case where the maxi- mum volume is set to 1.0, it will take 512 audio frames for this ramp to reach zero. note that a mute command is the same as setting the volume to zero, except that when the part is unm uted, the volume returns to its original value. these volume ramp times assume that the AD1954 is set for the fast volume ramp speed. if the slow setting is selected, it will take 8192 audio frames to reach zero from a setting of 2.0. correspondingly, it will take 4096 frames to reach 0 volume from the normal setting of 1.0. t he volume blocks are placed after the biquad filter sections to maximize the level of the signal that is passed through the filter sections. in a typical situation, the nominal volume setting might be ?5 db, allowing a substantial increase in volume when the user increases the volume. the AD1954 was designed with an analog dynamic range of >112 db, so that in the typical situation with the volume set to ?5 db, the signal-to-noise ratio at the output will still exceed 97 db. greater output dynamic ranges are possible if the compressor/limiter is used, since the post-compression gain parameter can boost the signal back up to a higher level. in this case, the compressor will prevent the output from clipping when the volume is turned up and the input signal is large. stereo image expander the image-enhancement processing is based on adi? patented phat stereo algorithm. the block diagram is shown below. 1khz first order lpf level left in right in left out right out + + figure 6. stereo image expander the algorithm works by increasing the phase shift for low fre- quency signals that are panned left or right in the stereo mix. since the ear is responsive to interaural phase shifts below 1 khz, this increase in phase shifts results in a widening of the stereo image. note that signals panned to the center are not processed, resulting in a more natural sound. there are two parameters that control the phat stereo algorithm: the level variable, which controls how much out-of-phase information is added to the left
rev. 0 AD1954 ?5 and right channels, and the cutoff frequency of the first order low-pass filter, which determines the frequency range of the added out-of-phase signals. for best results, the cutoff fre- quency should be in the range of 500 hz to 2 khz. these parameters are controlled by altering the parameter ram loca- tions that store the parameters spread_level and alpha_spread. the spread_level is a linear number in 2.20 format that multiplies the processed left-right signal before it is added to or subtracted from the main channels. the parameter alpha_spread is related to the cutoff frequency of the first order low-pass filter by the equation: alpha spread exp spread freq f s _. ? _ = ? ? ? ? ? ? 10 20 where exp is the exponential operator, spread_freq is the low-pass cutoff in hz, and f s is the audio sampling rate. note that the stereo spreading algorithm assumes that frequen- cies below 1 khz are present in the main satellite speakers. in some systems, the crossover frequency between the satellite and subwoofer speakers is quite high (>500 hz). in such a case, the stereo spreading algorithm will not be effective, since the frequencies that contribute to the spreading effect will come mostly from the subwoofer, which is a mono source. delay each of the three dac channels has a delay block that allows the user to introduce a delay of up to 165 audio samples. the delay values are programmed by entering the delay (in samples) into the appropriate location of the parameter ram. with a 44.1 khz sample rate, a delay of 165 samples corresponds to a time delay of 3.74 ms. since sound travels at approximately 1 foot/ms, this can be used to compensate for speaker placements that are off by as much as 3.74 feet. an additional 100 samples of delay are used in the look-ahead portion of the compressor/limiter but only for the main two channels. this can be used to increase the total delay for the left and right channels to 265 samples or 6 ms at 44.1 khz. main compressor/limiter the compressor used in the AD1954 is quite sophisticated and is comparable in many ways to the professional compressor/limiters used in the professional audio and broadcast fields. it uses rms/ peak detection with adjustable attack/hold/release, look-ahead compression, and table-based entry of the input/output curve for complete flexibility. the AD1954 uses two compressor/limiters: one in the subwoofer dac and one in the main left/right dac. it is well known that having independent compressors operating over different frequency ranges results in a superior perceived sound. with a single-band compressor, loud bass information will modulate the gain of the entire audio signal, resulting in suboptimal maximum perceived loudness as well as gain pumping or modulation effects. with independent compressors operating separately on the low and high frequencies, this problem is dramatically reduced. if the AD1954 is being operated in 2-channel mode, an extra path is added so that the subwoofer channel can be added back into the main channel. this maintains the advantage of using a two-band compressor, even in a 2.0 system configuration. figure 7 shows the traditional basic analog compressor/limiter. it uses a voltage-controlled amplifier to adjust gain and a feed- forward detector path using an rms detector with adjustable time constants, followed by a nonlinear circuit, to implement the desired input/output relationship. a simple compressor will have a single threshold above which the gain is reduced. the amount of compression above the threshold is called the compression ratio and is defined as db change in input/db change in output. for example, if the input to a 2:1 compres- sor is in creased by 2 db, the output will rise by 1 db for signals above the threshold. a single ?ard?threshold results in more audible behavior than a so-called ?oft-knee?compressor, where the compression is introduced more gradually. in an analog compressor, the soft-knee characteristic is usually made by using diodes in their exponential turn-on region. filter rms detector with db out compression curve nonlinear circuits vca with exp control threshold slope out figure 7. analog compressor the best analog compressors use rms detection as the signal amplitude detector. the only class of detectors that are not sensitive to the phase of the harmonics in a complex signal are rms detectors. the ear also bases its loudness judgment on the overall signal power and therefore using an rms detector results in the best audible performance. compressors that are based on peak detection, while good for preventing clipping, are generally quite poor when it comes to audible performance. rms detectors have a certain time constant that determines how rapidly they can respond to transient signals. there is always a trade-off between speed of response and distortion. figure 8 shows this trade-off. input waveform compressor envelope fa st time constant compressor envelope slow time constant figure 8. effect of rms time constant on distortion in the case of a fast-responding rms detector, the detector enve- lope will have a signal component in addition to the desired dc component. this signal component (which, for an rms detector, is at twice the input frequency) will result in harmonic distortion when multiplied by this detector signal.
rev. 0 AD1954 ?6 the AD1954 uses a modified rms algorithm to improve the relationship between acquisition time and distortion. it uses a peak-riding circuit together with a hold circuit to modify the rms signal, as shown in figure 9. this figure shows two envelopes. one has the harmonic distortion, as seen in the previous figure, and the other flatter envelope is the one produced by the AD1954. input waveform hold time, spi- programmable release time, spi- programmable figure 9. using the hold and release time feature using this idea of a modified rms algorithm, the true rms value is still obtained for all but the lowest frequency signals, while the distortion due to rms ripple is reduced. it also allows th e user to set the hold and release times of the compressor i ndependently. the detector path of the AD1954 is shown in figure 10. the rms detector is controlled by three parameters stored in the param- eter rms: the rms time constant, the hold time, and the release rate. the log output of the rms detector is applied to a look-up table with interpolation. the higher bits of the rms output form an offset into this table, and the lower bits are used to interpo- late between the table entries to form a high-precision gain word. the look-up table resides in the parameter ram and is loaded by the user to give the desired curve. the look-up table contains 33 data locations, and the lsb of the address into the look-up table corresponds to a 3 db change in the amplitude of the detector signal. this gives the user the ability to program an input/output curve over a 99 db range. for the main com pressor, the table resides in locations 110 to 142 in the spi parameter ram. look-up table linear interpolation modified rms detector with log output output to gain stage high bits (1lsb = 3db) low bits time constant hold release figure 10. gain derived from interpolated look-up table one subtlety of the table look-up involves the difference between the rms value of a sine wave and that of a square wave. if a full- scale square wave is applied to the AD1954, the rms value of this signal will be 3 db higher than the rms value of a 0 dbfs sine wave. therefore, the top table entry (location 142 for the main channel compressor) has been set to correspond to the rms value of a 0 dbfs square wave. since we would prefer to cali- brate ourselves to sine wave amplitudes, we will refer to this table entry as 3 db. therefore, the table will range from +3 db (location 142) to ?6 db (location 110). the entries in the table are linear gain words in 2.20 format. figure 11 shows an example of the table entries for a simple above-threshold compressor. input level ?3db/table entry output level ?db input level ?3db/table entry linear gain 1.0 desired compression curve figure 11. example of table entry for a given compression curve note that the maximum gain that can be entered in the table is 2.0 (minus 1 lsb). if more gain is required, the entire compres- sion curve may be shifted upward by using the post-compression gain block following the compressor/limiter. the AD1954 compressor/limiter also includes a look-ahead compression feature. the idea behind look-ahead compression is to prevent compressor overshoots by applying some digital delay to the signal before the gain-control multiplier but not to the detector path. in this way, the detector can acquire the new amplitude of the input signal before the signal actually reaches the multiplier. a comparison of a tone burst fed to a conventional compressor versus a look-ahead compressor is shown in figure 12. conventional compressor gain look-ahead compressor gain hold time figure 12. conventional compression vs. look-ahead c ompression
rev. 0 AD1954 ?7 in the look-ahead compressor, the gain has already been reduced by the time that the tone-burst signal arrives at the multiplier input. note that when using a look-ahead compressor, it is important to set the detector hold time to a value that is at least the same as the look-ahead delay time or else the compressor release will start too soon, resulting in an expanded ?ail?of a tone-burst signal. the complete flow of the left/right dynamics processor is shown in figure 13. look-up table linear interpolation modified rms detector with log output high bits (1lsb = 3db) low bits time constant hold release delay delay spi-programmable look-ahead delay post-compression gain, spi- programmable up to 30db 2 (l+r) figure 13. complete dynamics flow, main channels the detector path works from the sum of the left and right channels ((l + r)/2). this is the normal way that compressors are built and counts on the fact that the main instruments in any stereo mix are seldom recorded deliberately out of phase, espe- cially in the lower frequencies that tend to dominate the energy spectrum of real music. the compressor is followed by a block known as post-compression gain. most compressors are used to reduce the dynamic range of music by lowering the gain during loud signal passages. this results in an overall loss of volume. this loss can be made up by introducing gain after the compressor. in the AD1954, the coefficient format used is 2.20, which has a maximum floating- point representation of slightly less than 2.0. this means that the maximum gain that can be achieved in a single instruction is 6 db. to get more gain, the program in the AD1954 uses a cascade of five multipliers to achieve up to 30 db of post-compression gain. to program the compressor/limiter, the following formulas may be used to determine the 22-bit numbers (in 2.20 format) to be entered into the parameter ram. rms time constant this can be best expressed by entering the time constant in terms of db/sec raw release rate (without the peak-riding circuit). the attack rate is a rather complicated formula that depends on the change in amplitude of the input sine wave. rms tconst parameter release rate f s __ . . = () ? ? ? ? ? ? 10 10 10 0 where rm s_ t const_parameter = the fractional number to enter into the spi ram (after converting to 22-bit 2.20 format), and the release_rate = the release rate of the raw rms detector in db/sec. this must be negative, and f s = the audio sample rate. rms hold time rms holdtime parameter f hold time s __ int _ = () where rm s_ h oldtime_parameter = the integer number to enter into the spi ram, f s = the audio sample rate, hold_time = the abso- lute time to wait before starting the release ramp -down of the detector output, and int() = the integer part of the expression. rms release rate rms decay parameter rms decay __ int _ / . = () 0 137 where rms_decay_parameter = the decimal integer number to enter into the spi ram, rms_decay = the decay rate in db/sec, and int() = the integer part of the expression. look-ahead delay lookahead delay parameter lookahead delay f s __ _ = where lookahead_delay = the predictive compressor delay in abso lute time, f s = the audio sample rate, and the maximum lookahead_delay_parameter value is 100. post-compression gain post compression gain parameter post compression gain linear ___ ___/ = () 15 where p ost_compression_gain_linear is the linear post-compression gain and ^ = the raise to the power. subwoofer compressor/limiter the subwoofer compressor/limiter differs from the left/right compressor in the following ways: 1. the subwoofer compressor operates on a weighted sum of the left and right inputs (aa left + bb right), where aa and bb are both programmable. 2. the detector input has a biquad filter in series with the input in order to implement frequency-dependent compres- sion thresholds. 3. there is no predictive compression since presumably the input signals are filtered to pass only low frequencies and therefore transient overshoots are not a problem. the subwoofer compressor signal flow is shown in figure 14. look-up table linear interpolation modified rms detector with log output high bits (1lsb = 3db) low bits time constant hold release v in _sub = k1 left_in + k2 right_in post-compression gain, spi- programmable up to 30db biquad filter figure 14. signal flow for subwoofer compressor the biquad filter before the detector can be used to implement a frequency-dependent compression threshold. for example, assume that the overload point of the woofer is strongly fre quency dependent. in this case, one would have to set the compressor threshold to a value that corresponded to the most sensitive overload frequency of the woofer. if the input signal happened to be mostly in a frequency range where the woofer was not so sensitive to overload, then the compressor would be too pessimistic and the volume of the woofer would be reduced.
rev. 0 AD1954 ?8 if, on the other hand, the biquad filter were designed to follow the woofer excursion curve of the speaker, then the volume of the woofer could be maximized under all conditions. this is illustrated in figure 15. 20hz 200hz frequency w oofer excursion biquad response 20hz 200hz frequency figure 15. optimizing woofer loudness using the s ubwoofer rms biquad filter when using a filter in front of the detector, a confusing side- effect occurs. if one measures the frequency response by using a swept sine wave with an amplitude large enough to be above the compressor threshold, the resulting frequency response w ill not look flat. however, this is not real in the sense that, as the sine wave is swept through the system, the gain is being slowly modulated up and down according to the response of the biquad filter in front of the detector. if one measures the response using a pink-noise generator, the resu lt will look much better, since the detector will settle on only one gain value. the perceptual effect of the swept sine wave test is not at all what would be predicted by simply looking at the frequency response curve; it is only the signal-path filters that will affect the perception of the fre quency response, not the detector-path filters. de-emphasis filtering the standard for encoding cds allows the use of a pre-empha- sis cu rve during encoding, which must be compensated for by a de-emphasis curve during playback. the de-emphasis curve is defined as a first order shelving filter with a single pole at (1/(2 50 s)) followed by a single zero at (1/(2 15 s)). this curve may be accurately modeled using a first order digital filter. this filter is included in the AD1954; it is not part of the bank of biquad filters, and so does not take away from the number of available filters. since the specification of the de-emphasis filter is based on an analog filter, the response of the filter should not depend on the incoming sampling rate. however, when the de-emphasis filter is implemented digitally, the response will scale with the sampling rate unless the filter coefficients are altered to suit each possible input sampling rate. for this reason, the AD1954 includes three separate de-emphasis curves: one each for sampling rates of 32 khz, 44.1 khz, and 48 khz. these curves are selected by writing to bits 5 and 4 of control register 1 over the spi port. alternatively, the 44.1 khz curve can be called upon using the deemp/ sdata_aux pin. this pin is included for compatibility with cd decoder chips that have a de-emphasis output pin. using the sub reinjection paths for systems with no subwoofer many systems will not use a subwoofer but would still benefit from two-band compression/limiting. this can be accommo dated by using sub reinjection paths in the program flow. these param- eters are programmed by entering two numbers (in 2.20 format) into the parameter ram. note that if the biquad filters are not properly designed, the frequency response at the crossover point may not be flat. many crossover filters are designed to be flat in the sense of adding the powers together, but nonflat if the sum is done in voltage mode. the user must take care to design an appropriate set of crossover filters. interpolation filters the left and right channels have a 128:1 interpolation filter with 75 db stop-band attenuation that precedes the digital sigma- delta modulator. this filter has a group delay of approximately 24.1875/fs taps, where f s is the sampling rate. the sub channel does not use an interpolation filter. the reason for this (besides saving valuable mips) is that it is expected that the bandwidth of the sub output will be limited to less than 1 khz. with no inter- polation filter, the first ?mage?will therefore be at 43.1 khz (which is f s ?1 khz for cd audio). the standard external filter used for both the main and sub channels is a third order, single op amp filter. if the cutoff frequency of the external subwoofer filter is 2 khz, then there are more than 4 octaves between 2 khz and the first image at 43.1 khz. a third order filter will roll-off by approximately 18 db/oct 4 octaves = 72 db attenuation. this is approximately the same as the digital attenu ation used in the main channel filters, so no internal interpolation filter is required to remove the out-of-band images. note that by having interpolation filters in the main channels but not the subwoofer channel, there is a potential time-delay mi smatch between the main and sub channels. the group delay of the digital interpolation filters used in the main left/right chan- nels is about 0.5 ms. this must be compared to the group delay of the extern al analog filter used in the subwoofer path. if the group-delay mismatch causes a frequency response error (when the two signals are ?coustically added?, then the programmable d elay feature can be used to put extra delay in either the subwoofer path or the main left/right path. spi port overview the AD1954 has many different control options. most signal- processing parameters are controlled by writing new values to the parameter ram using the spi port. other functions, such as volume and de-emphasis filtering, are programmed by writing to the spi control registers. the spi port uses a 4-wire interface, consisting of clatch, cclk, cdata, and cout signals. the c latch signal goe s low at the beginning of a transaction and high at the end of a transaction. the cclk signal latches the serial input data on a low-to- high transition. the cdata signal carries the serial input data, and the cout signal is the serial output data. the cout signal remains tri-stated until a read operation is requested. this allows other spi-compatible peripherals to share the same readback line. the spi port is capable of full read/write operation for all of the memories (parameter and program) and some of the spi regis ters (control register 1 and the data capture registers). the memories may be accessed in both a single-address mode or in burst mode. all spi transactions follow the same basic format that is shown in table i. table i. spi word format byte 0 byte 1 byte 2 byte 3 byte 4 00000, r/wb, adr[9:8] adr[7:0] data data data
rev. 0 AD1954 ?9 the r/wb bit is low for a write and high for a read operation. the 10-bit address word is decoded into either a location in one of the two memories (parameter or program) or one of the spi registers. the number of data bytes varies according to the register or memory being accessed. in burst-write mode (available for loading the rams only), an initial address is given followed by a continuous sequence of data for consecutive ram locations. the detailed data format diagram for continuous-mode opera tion is given in spi read/write data formats. a sample timing diagram for a single spi write operation to the parameter ram is shown in figure 16. a sample timing diagram of a single spi read operation is shown in figure 17. the cout pin goes from three -state to driven at the beginning of byte 2. bytes 0 and 1 contain the address and r/w bit, and bytes 2? carry the data. the exact format is shown in t ables viii to xix. byte 0 byte 1 byte 4 cdata cclk clatch figure 16. sample of spi write format (single-write mode) byte 0 cdata cclk clatch cout byte 1 hi-z data xxx data data hi-z figure 17. sample of spi read format (single-write mode) the AD1954 has several mechanisms for updating signal- processing parameters in realtime without causing loud pops or clicks. in cases where large blocks of data need to be downloaded, the dsp core can be shut down and new data loaded, and then the core can be re started. the shutdown and restart mechanisms employ a gradual volume ramp to prevent clicks and pops. in cases where only a few parameters need to be changed ( e.g., a single biquad filter), a safeload mechanism is used that allows a block of spi registers to be transferred to the parameter ram within a single audio frame while the core is running. the safeload mode uses internal logic to prevent contention between the dsp core and the spi port. spi address decoding table ii shows the address decoding used in the spi port. the spi address space encompasses a set a registers and two rams, one for holding signal-processing parameters and one for holding the program instructions. both of the rams are loaded on power-up from on-board boot roms.
rev. 0 AD1954 ?0 table ii. spi port address decoding spi address register name read/write word length 0?55 parameter ram write: 22 bits read: 22 bits 256 spi control register 1 write: 11 bits read: 2 bits 257 spi control register 2 write: 9 bits read: n/a 258 volume left write: 22 bits read: n/a 259 volume right write: 22 bits read: n/a 260 volume sub write: 22 bits read: n/a 261 data capture (spi out) #1 write: 9-bit program counter value, 2-bit register address read: 24 bits 262 data capture (spi out) #2 write: 9-bit program counter value, 2-bit register address read: 24 bits 263 data capture (serial out) left write: 9-bit program counter value, 2-bit register address read: n/a 264 data capture (serial out) right write: 9-bit program counter value, 2-bit register address read: n/a 265 parameter ram safe load register 0 write: 8-bit parameter ram address, 22-bit parameter data read: n/a 266 parameter ram safe load register 1 write: 8-bit parameter ram address, 22-bit parameter data read: n/a 267 parameter ram safe load register 2 write: 8-bit parameter ram address, 22-bit parameter data read: n/a 268 parameter ram safe load register 3 write: 8-bit parameter ram address, 22-bit parameter data read: n/a 269 parameter ram safe load register 4 write: 8-bit parameter ram address, 22-bit parameter data read: n/a 270?10 unused 511 test register write: 8 bits read: n/a 512?024 program ram write: 35 bits read: 35 bits control register 1 control register 1 is an 11-bit register that controls serial modes, de-emphasis, mute, power-down, and spi-to-memory transfers. table iii documents the contents of this register. bit 11 controls the functions of the deemp/sdata_aux pin. the default setting is 0, which corresponds to the de-emphasis function. more information is available in the pin functions section. the word length bits are used in right-justified serial modes to determine where the msb is located relative to the start of the audio frame. the serial mode bits select one of four modes, which are discussed in the serial data input port section. the de-emphasis bits turn on the internal de-emphasis filter for one of three possible sample rates. the halt program bit is used to initiate a volume ramp-down fo llowed by a shutdown of the dsp core. the user may poll for t his operation to complete by reading bit 1 of control register 1. soft mute is used to initiate a volume ramp-down sequence. if the initial volume was set to 1.0, this operation will take 512 audio frames to complete. when this bit is de-asserted, a ramp- up sequence is initiated until the volume returns to its original setting. the initiate safe-transfer bit will request a data transfer from the spi safeload registers to the parameter ram. the safeload registers contain address data pairs and only those registers that have been written to since the last transfer opera- tion will be uploaded. the user may poll for this operation to complete by reading bit 0 of control register 1. the safeload mechanism section goes into more detail on this feature. the soft power-down bit stops the internal clocks to the dsp core but does not reset the part. the digital power consumption is reduced to a low level when this bit is asserted. reset can only be asserted using the external reset pin. the enable dcsout bit is used to turn on the data capture serial o ut pin. this pin may be used to send data that is captured using the data capture feature to external devices, such as an additional stereo dac. the data capture registers section gives more infor- mation about the data capture feature. when a read operation is performed on control register 1, two bits are returned, as shown in table iv.
rev. 0 AD1954 ?1 table iii. control register 1 write definition register bits function 11 de-emphasis/auxiliary serial input pin select (1 = auxiliary serial input) 10 halt program (1 = halt) 9 initiate safe transfer (1 = transfer) 8e nable dcsout output pin (1 = enable) 7 soft mute (1 = start mute sequence) 6 soft power-down (1 = power-down) 5:4 de-emphasis curve select 00 = none 01 = 44.1 khz 10 = 32 khz 11 = 48 khz 3:2 serial in mode 00 = i 2 s 01 = right-justified 10 = dsp 11 = left-justified 1:0 word length 00 = 24 bits 01 = 20 bits 10 = 16 bits 11 = 16 bits table iv. control register 1 read definition register bits function 1d sp core shutdown complete 1 = shutdown complete 0 = not shut down 0 safe memory load complete 1 = complete (note: cleared after read) 0 = not complete bit 0 is asserted when all requested safeload registers have been transferred to the parameter ram. it is cleared after the read operation is complete. bit 1 is asserted after the requested shutdown of the dsp is completed. when this bit is set, the user is free to write or read any ram location without causing an audio pop or click. table v. control register 2 write definition register bits function 9v olume ramp speed 1 = 160 ms full ramp time 0 = 20 ms full ramp time 8s erial port output enable 1 = enabled 0 = disabled 7:6 serial port input select 00 = in0 01 = in1 10 = in2 11 = na 5:4 mclk input select 00 = mclk0 01 = mclk1 10 = mclk2 11 = na 3r eserved 2 mclk in frequency select 0 = 512 f s 1 = 256 f s 1:0 mclk out frequency select 00 = disabled 01 = 512 f s 10 = 256 f s 11 = mclk_out = mclk_in (feedthrough) control register 2 table v documents the contents of control register 2. bits 1 and 0 set the frequency of the mclkout pin. if these bits are set to 00, then the mclkout pin is disabled (default). when set to 01, the mclkout pin is set to 512 f s , which is the same as the internal master clock used by the dsp core. when set to 10, this pin is set to 256 f s , derived by dividing the internal dsp clock by 2. in this mode, the output 256 f s clock will be inverted with respect to the input 256 f s clock. this is not the case with the feedthrough mode. when set to 11, the mclkout pin mirrors the selected mclk input pin (it? the output of the mclk mux selector). note that the internal dsp master clock may either be the same as the selected mclk pin (when mclk frequency s elect is set to 512 f s mode) or may be derived from the mclk pin using an internal clock doubler (when mclk frequency select is set to 256 f s ). bit 2 selects one of two possible mclk input frequencies. when set to 0 (default), the mclk frequency is set to 512 f s . in this mode, the internal dsp clock and the external mclk are at the same frequency. when set to 1, the mclk freque ncy is set to 256 f s , and an internal clock doubler is used to generate the dsp clock. bits 5 and 4 select one of three clock input sources using an internal mux. to avoid click and pop noises when switching mclk sou rces, it is recommended that the user put the dsp core in shutdown before switching mclk sources. bits 7 and 6 select one of three serial input sources using an internal mu x. each source selection includes a separate sdata, lrclk,
rev. 0 AD1954 ?2 and bclk input. to avoid click and pop noises when switching serial sources, it is recommended that the user put the dsp core in shutdown before writing to these bits. bit 8 is used to enable the three serial output pins. these pins are connected to the output of the serial input mux, which is set by bits 7 and 6. the default is 0 (disabled). volume registers the AD1954 contains three 22-bit volume registers: one each for the left, right, and subwoofer channels. these registers are special because when the volume is changed from an initial value to a new value, a linear ramp is used to interpolate between the two values. this feature prevents audible clicks and pops when changing volume. the ramp is set so that it takes 512 audio frames to decrement from a volume of 1.0 (default) down to 0 (muted). the volume registers are formatted in 2.20 two? complement, meaning that 01000000000000000000 is interpreted as 1.0. negative values can also be written to the volume register, causing an inversion of the signal. negative values work as expected with the ramp feature; to go from +1.0 to ?.0 will take 1024 lrclks, and the volume will pass-through 0 on the way. parameter ram contents table vi shows the contents of the parameter ram. the parameter ram is 22 bits wide and occupies spi addresses 0?55. the low addresses of the ram are used to control the biquad filters. there are 22 biquad filters in all, and each biquad has five coefficients, resulting in a total memory usage of 110 coefficients. there are also two tables of 33 coefficients, each that define the main and subcompressor input/output characteristics. these are loaded with 1.0 on power-up, resulting in no compression. other ram entries control other compressor characteristics, as well as delay and spatialization settings. the parameter ram is initialized on power-up by an on-board boot rom. the default values (shown in the table) yield no equalization, no compression, no spatialization, no delay, and normal detector time constants in the compressor sections. the functionality of the AD1954 on power-up is basically that of a normal audio dac with no signal-processing capability. the data format of the parameter ram is two? complement 2.20 format. this means that the coefficients may range from +2.0 (? lsb) to ?.0, with 1.0 represented by the binary word 01000000000000000000. table vi. parameter ram contents default value in fractional address function 2.20 format 0 iir0 left b0 1.0 1 iir0 left b1 0 2 iir0 left b2 0 3 iir0 left a1 0 4 iir0 left a2 0 5 iir1 left b0 1.0 6 iir1 left b1 0 7 iir1 left b2 0 8 iir1 left a1 0 9 iir1 left a2 0 10 iir2 left b0 1.0 11 iir2 left b1 0 12 iir2 left b2 0 13 iir2 left a1 0 14 iir2 left a2 0 15 iir3 left b0 1.0 16 iir3 left b1 0 17 iir3 left b2 0 18 iir3 left a1 0 19 iir3 left a2 0 20 iir4 left b0 1.0 21 iir4 left b1 0 22 iir4 left b2 0 23 iir4 left a1 0 24 iir4 left a2 0 25 iir5 left b0 1.0 26 iir5 left b1 0 27 iir5 left b2 0 28 iir5 left a1 0 29 iir5 left a2 0 30 iir6 left b0 1.0 31 iir6 left b1 0 table vi. parameter ram contents (continued) default value in fractional address function 2.20 format 32 iir6 left b2 0 33 iir6 left a1 0 34 iir6 left a2 0 35 iir0 right b0 1.0 36 iir0 right b1 0 37 iir0 right b2 0 38 iir0 right a1 0 39 iir0 right a2 0 40 iir1 right b0 1.0 41 iir1 right b1 0 42 iir1 right b2 0 43 iir1 right a1 0 44 iir1 right a2 0 45 iir2 right b0 1.0 46 iir2 right b1 0 47 iir2 right b2 0 48 iir2 right a1 0 49 iir2 right a2 0 50 iir3 right b0 1.0 51 iir3 right b1 0 52 iir3 right b2 0 53 iir3 right a1 0 54 iir3 right a2 0 55 iir4 right b0 1.0 56 iir4 right b1 0 57 iir4 right b2 0 58 iir4 right a1 0 59 iir4 right a2 0 60 iir5 right b0 1.0 61 iir5 right b1 0 62 iir5 right b2 0 63 iir5 right a1 0
rev. 0 AD1954 ?3 * the default decay time of the hold/release circuit is set fast enough that the decay is dominated by the time constant of the r ms detector. table vi. parameter ram contents (continued) default value in fractional address function 2.20 format 64 iir5 right a2 0 65 iir6 right b0 1.0 66 iir6 right b1 0 67 iir6 right b2 0 68 iir6 right a1 0 69 iir6 right a2 0 70 iir0 xover left b0 1.0 71 iir0 xover left b1 0 72 iir0 xover left b2 0 73 iir0 xover left a1 0 74 iir0 xover left a2 0 75 iir1 xover left b0 1.0 76 iir1 xover left b1 0 77 iir1 xover left b2 0 78 iir1 xover left a1 0 79 iir1 xover left a2 0 80 iir0 xover right b0 1.0 81 iir0 xover right b1 0 82 iir0 xover right b2 0 83 iir0 xover right a1 0 84 iir0 xover right a2 0 85 iir1 xover right b0 1.0 86 iir1 xover right b1 0 87 iir1 xover right b2 0 88 iir1 xover right a1 0 89 iir1 xover right a2 0 90 iir0 xover sub b0 1.0 91 iir0 xover sub b1 0 92 iir0 xover sub b2 0 93 iir0 xover sub a1 0 94 iir0 xover sub a2 0 95 iir1 xover sub b0 1.0 96 iir1 xover sub b1 0 97 iir1 xover sub b2 0 98 iir1 xover sub a1 0 99 iir1 xover sub a2 0 100 iir2 xover sub b0 1.0 101 iir2 xover sub b1 0 102 iir2 xover sub b2 0 103 iir2 xover sub a1 0 104 iir2 xover sub a2 0 105 iir sub rms b0 1.0 106 iir sub rms b1 0 107 iir sub rms b2 0 108 iir sub rms a1 0 109 iir sub rms a2 0 110 ?142 main compressor look-up table base 143 main compressor attack/rms time constant 144 main post-compressor gain 145 ?177 subwoofer compressor look-up table base 178 subcompressor attack/rms time constant 179 post-compressor gain (sub) 180 high-pass filter cutoff frequency 181 main compressor look-ahead delay 182 delay left 183 delay right 184 delay sub 185 stereo spreading coefficient 186 stereo spreading frequency control 187 subwoofer reinjection to main left 188 subwoofer reinjection to main right 189 subwoofer channel input gain from left in 190 subwoofer channel input gain from right in 191 main detector hold time, samples (4095 max) 192 sub detector hold time, samples (4095 max) 193 main detector decay time 194 sub detector decay time 195-255 unused table vi. parameter ram contents (continued) default value in fractional address function 2.20 format 1.0 (all) 5.75 10 ? (120 db/sec) 1.0 1.0 (all) 5.75 10 ? (120 db/sec) 1.0 3.92 10 ? 0 0 0 0 0 0.112694 0.0 0.0 0.5 0.5 0 0 0.069611 (10000 db/sec) * 0.069611 (10000 db/sec) *
rev. 0 AD1954 ?4 options for parameter updates the parameter and program rams can be written and read using one of several methods. 1. direct read/write. this method allows direct access to the rams. since the rams are also being used during realtime dsp operation, a glitch will likely occur at the output. this method is not recommended. 2. direct read/write after core shutdown. this method avoids the glitch while accessing the internal rams by first shut- ting down the core. this is recommended for transferring large am ounts of data, such as initializing the parameter ram at power-up or downloading a completely new pro- gram. these transfers can be sped up by using burst mode, where an initial address followed by blocks of data are sent to the ram. 3. safeload writes. this is where up to five spi registers are loaded with address/data intended for the parameter ram. the data is then transferred to the requested address when the ram is not busy. this method can be used for dy- namic updates while live program material is playing through the AD1954. for example, a complete update of one biquad section can occur in one audio frame while the ram is not busy. this method is not available for writing to the program ram or control registers. the next section discusses these options in more detail. soft shutdown mechanism when writing large amounts of data to the program or parameter ram, the processor core should be halted to prevent unpleasant noises from appearing at the audio output. figure 18 shows a graphical representation of this mechanism? volume envelope. points a? are referenced in the following description. bit 10 in s erial control register 0 (processor shutdown bit) will shut down the processor core. when the processor shutdown bit is asserted (a), an automatic volume ramp-down sequence (b) lasting from 10 ms?0 ms will occur, followed by a shutdown of the core. this method of shutting down the core prevents pops or clicks from occurring. after the shutdown is complete, bit 1 in control register 1 will be set. the user can either poll for this bit to be set or just wait for a period longer than 20 ms. once the core is shut down (c), the parameter or program rams may be written or read freely. to ease the transfer of large blocks of sequential data, a block transfer mode is supported where a starting address followed by a stream of data is sent to the memory. the address into the memory will be automatically incremented for each new write. this mode is documented in the spi read/ write data formats section of this data sheet. once the data has been written, the shutdown bit can be cleared (d). the processor then will initiate a volume ramp-up sequence that lasts for 10ms?0 ms. again, this reduces the chance of any pop or click noise from occurring. note that this shutdown sequence assumes that the part is set to the fast volume ramp speed (control register 2, bit 9). if the slow ramp speed is set, the volume may not reach zero before the part enters shutdown and a click or pop may be heard. safeload mechanism many applications require realtime control of filter characteristics, such as bass/treble controls and parametric or graphic equaliza- tion. to prevent instability from occurring, all of the parameters of a particular biquad filter must be updated at the same time; otherwise, the filter could execute for one or two audio frames with a mixture of old and new coefficients. this mix of old and new could cause temporary instability, leading to transients that could take a long time to decay. the method used in the AD1954 to eliminate this problem is to load a set of five registers in the spi port with the desired param- eter ram address and data. five registers are used because each biquad filter has five coefficients. once these registers are loaded, the initiate safe transfer bit in spi control register 1 is set. once this bit is set, the processor waits for a period of time in the program sequence where the parameter ram is not being accessed for at least five consecutive instruction cycles. when the program counter reaches this point, the parameter ram is written with five new data values at addresses corresponding to those that were entered in the safeload registers. when the operation is complete, bit 0 of control register 1 is set. this bit may be polled by the external microprocessor until a 1 is read. this bit will be reset on a read operation. the polling operation is not required; the safeload mechanism guarantees that the transfer will be complete within one audio frame. the safeload logic automatically sends only those safeload regis ters that have been written to since the last safeload operation. for example, if only two parameters are to be sent, then it is only necessary to write to two of the five safeload registers. when the request safe transfer bit is asserted, only those two registers will be sent; the other three registers are not sent and can still hold old or invalid data. the safeload mechanism is not limited to uploading biquad coefficients; any set of five values in the parameter ram may be updated in the same way. this allows realtime adjustment of the compressor/limiter, delay, or stereo spreading blocks. summary of ram modes table vii shows the sizes and available modes of the parameter ram and the program ram. ad c b figure 18. recommended sequences for complete parameter of program ram upload using shutdown mechanism
rev. 0 AD1954 ?5 table viii. parameter ram read/write format (single address) byte 0 byte 1 byte 2 byte 3 byte 4 00000, r/wb, adr[9:8] adr[7:0] 00, param[21:16] param[15:8] param[7:0] table x. program ram read/write format (single address) byte 0 byte 1 byte 2 byte 3 byte 4 byte 5 byte 6 00000, r/wb, adr[9:8] adr[7:0] 00000, prog[34:32] prog[31:24] prog[23:16] prog[15:8] prog[7:0] table xii. spi control register 1 write format byte 0 byte 1 byte 2 byte 3 00000, r/wb, adr[9:8] adr[7:0] 0000, bit[11:8] bit[7:0] table xiii. spi control register 1 read format byte 0 byte 1 byte 2 00000, r/wb, adr[9:8] adr[7:0] 000000, bit[1:0] table xiv. spi control register 2 write format byte 0 byte 1 byte 2 byte 3 00000, r/wb, adr[9:8] adr[7:0] 000000, bit[9:8] bit[7:0] table xv. spi volume register write format byte 0 byte 1 byte 2 byte 3 byte 4 000000, adr[9:8] adr[7:0] 00, volume[21:16] volume[15:8] volume[7:0] adr byte 5 byte 8 byte 6 byte 9 byte 7 byte 10 adr + 1 adr + 2 table ix. parameter ram block read/write format (burst mode) byte 0 byte 1 byte 2 byte 3 byte 4 00000, r/wb, adr[9:8] adr[7:0] 00, param[21:16] param[15:8] param[7:0] table xi. program ram block read/write format (burst mode) byte 0 byte 1 byte 2 byte 3 byte 4 byte 5 byte 6 00000, r/wb, adr[9:8]adr[7:0] 00000, prog[34:32] prog[31:24] prog[23:16] prog[15:8] prog[7:0] adr byte 7 byte 12 byte 8 byte 13 byte 9 byte 14 byte 10 byte 15 byte 11 byte 16 adr + 1 adr + 2 table vii. read/write modes memory size spi address range read write burst mode available write modes parameter ram 256 22 0?55 yes yes yes direct write, write after core shutdown, safeload write program ram 512 35 512?023 yes yes yes direct write, write after core shutdown
rev. 0 AD1954 ?6 table xvi. data capture register write format byte 0 byte 1 byte 2 byte 3 00000, r/wb, adr[9:8] adr[7:0] 00000, progcount[8:6] 1 progcount[5:0], regsel[1:0] 1, 2 notes 1 progcount[8:0] = value of program counter where trap occurs (see table xx). 2 regsel[1:0] selects one of four registers (see data capture register section). table xvii. data capture serial out register (address and register select) write format byte 0 byte 1 byte 2 byte 3 00000, r/wb, adr[9:8] adr[7:0] 00000, progcount[8:6] 1 progcount[5:0], regsel[1:0] 1, 2 notes 1 progcount[8:0] = value of program counter where trap occurs (see table xx). 2 regsel[1:0] selects one of four registers (see data capture register section). table xviii. data capture read format byte 0 byte 1 byte 2 byte 3 byte 4 byte 5 00000, r/wb, adr[9:8] adr[7:0] 00000000 data[23:16] data[15:8] data[7:0] table xix. safeload register write format byte 0 byte 1 byte 2 byte 3 byte 4 byte 5 00000, r/wb, adr[9:8] adr[7:0] paramadr[7:0] 00, param[21:16] param[15:8] param[7:0] spi read/write data formats the read/write formats of the spi port are designed to be byte oriented. this allows for easy programming of common microcontroller chips. to fit into a byte-oriented format, 0s are appended to the data fields to extend the data-word to the next multiple of 8 bits. for example, 22-bit words written to the spi parameter ram are appended with two leading zeroes to reach 24 bits (3 bytes), and 35-bit words w ritten to the program ram are appended with five zeros to reach 40 bits (5 bytes). these zero-extended data fields are appended to a 2-byte field consisting of a read/write bit and a 10-bit address. the spi port knows how many data bytes to expect based on the address that is received in the first two bytes. the total number of bytes for a single-location spi write command can vary from 4 bytes (for a control register write) to 7 bytes (for a program ram write). block writes may be used to fill contiguous locations in program ram or parameter ram. initialization power-up sequence the AD1954 has a built-in power-up sequence that initializes the contents of the internal rams. during this time, the contents of the internal program boot rom are copied to the internal program ram memory, and likewise, the spi parameter ram is filled with values from its associated boot rom. the data memories are also cleared during this time. the boot sequence lasts for 1024 mclk cycles and starts on the rising edge of the resetb pin. since the boot sequence requires a stable master clock, the user should avoid writing to or reading from the spi registers during this period of time. note that the default power-on state of the internal clock mode circuitry is 512 f s , or about 24 mhz for normal audio sample rates. this mode bypasses all the internal clock doublers and allows the external master clock to directly operate the dsp core. if the external master clock is 256 f s , then the boot se- quence will operate at this redu ced clock rate and take slightly longer to complete. after the boot sequence has fin ished, the clock modes may be set via the spi port. for example, if the external master clock frequency is 256 f s clock, the boot sequence would take 1024 256 f s clock cycles to complete, after which an spi write could occur to put the AD1954 in 256 f s mode. the default state of the mclk input selector is mclk0. since this input selector is controlled using the spi port, and the spi port cannot be written to until the boot sequence is complete, there must be a stable master clock signal present on the mclk0 pin at startup. setting the clock mode the AD1954 contains a clock doubler circuit that is used to generate an internal 512 f s clock when the external clock is 256 f s . the clock mode is set by writing to bit 2 of control register 2. when the clock mode is changed, it is possible that a glitch will occur on the internal mclk signal. this may cause the proces- sor to inadvertently write an incorrect value into the data ram, which could cause an audio pop or click sound. to prevent this, it is recommended that the following procedure be followed: 1. assert the soft power-down bit (bit 6 in control register 1) to stop the internal mclk. 2. write the desired clock mode into bit 2 of control register 2. 3. wait at least 1 ms while the clock doublers settle. 4. de-assert the soft power-down bit.
rev. 0 AD1954 ?7 an alternative procedure is to initiate a soft shutdown of the processor core by writing a 1 to the halt program bit in control register 1. this initiates a volume ramp-down sequence followed by a shutdown of the dsp core. once the core is shut down (which can be verified by reading bit 1 from control register 1 or by waiting at least 20 ms), the new clock mode can be programmed by writing to bit 2 of control register 2. the dsp core can then be restarted by clearing the halt program bit in control register 1. setting the data and mclk input selectors the AD1954 contains input selectors for both serial data inputs and the mclk input. this allows the AD1954 to select a variety of input and clock sources with no external hardware required. these input selectors are controlled by writing to spi control register 2. when the data source or mclk source is changed by writing to the spi port, it is possible that a pop or click will occur in the audio. to prevent this noise, the core should be shut down by writing a 1 to the halt program bit in control register 1. this initiates a volume ramp-down sequence followed by a shutdown of the dsp core. once the core is shut down (which can be verified by reading bit 1 from control register 1 or by waiting at least 20 ms after the halt program command is issued), the new data or mclk source can be programmed by writing to control register 2. the dsp core can then be restarted by clearing the halt program bit in control register 1. data capture registers the AD1954 incorporates a feature called data capture. using this feature, any node in the signal processing flow m ay be sent to either an spi-readable register or a dedicated serial output pin. this allows the basic functionality of the AD1954 to be ex- tended to a larger number of channels. alternatively, it can be used to monitor and display information about signal levels or compressor/limiter activity. the AD1954 contain s four i ndependent data capture registers. two of these registers transfer their data to the data capture serial output (dcsout) pin. the serial data format of this pin is the same as the serial data format used for the main digital inputs, and the lrclk and bclk signals can therefore be used as frame sync and bit clock signals. this pin is primarily intended to feed signals to an external dac or dsp chip to extend the number of channels that the internal dsp can access. the other two registers may be read back over the spi port and can be used for a variety of purposes. one example might be to access the db output of the internal rms detector to run a front- panel signal level display. a sample system is shown in figure 19. for each of the four data capture registers, a capture count and a register select must be set. the capture count is a number be tween 0 and 511 that corresponds to the program step number where the capture will occur. the register-select field programs one of four registers in the dsp core that will be transferred to the data capture register when the program counter equals the cap ture count. the register select field is decoded as follows: 00: multiplier output (mult_out) 01: output of db conversion block (db_out) 10: multiplier data input (mdi) 11: multiplier coefficient input (mci) the capture count and register select bits are set by writing to one of the four data capture registers at the following spi addresses: 261: spi data capture setup register 1 262: spi data capture setup register 2 263: data capture serial out setup register 1 264: data capture serial out setup register 2 the format of the captured data varies according to the register select fields. data captured from the mult_out setting is in 1.23 two? complement format so that a full-scale input signal will produce a full-scale digital output (assuming no processing). if the parameters are set such that the input-to-output gain is more than 0 db, then the digital output will be clipped. data captured from the db_out setting is in 5.19 format, where the actual rms db level is equal to ?7 + (3 db_out ). in this equation, db_out is the value that is captured. it fol- lows that in this data format, the actual output readings will range from ?7 to +9 db. the AD1954 uses the convention that 0 db is the rms value of the full-scale digital signal. data captured using the mdi setting is in 3.21 format. a 0 db digital input will produce a ?2 db digital output, assuming the AD1954 is set for no processing. data captured using the mci setting is in 2.20 format. this data is generally a signal gain or filter coefficient, and therefore it does not make sense to talk about the input-to-output gain. a coefficient of 01000000000000000000 corresponds to a gain of 1.0. the data that must be written to set up the data capture is a concatenation of the 9-bit program count index with the 2-bit register select field. refer to t able xx to find the capture count and register select numbers that correspond to the desired point to be monitored in the signal-processing flow. the spi capture registers can be accessed by reading from spi l ocations 261 (for spi capture register 1) or 262 (for spi capture register 2). the other two data capture registers (data- capture serial-out) automatically transfer their data to the data capture serial out (dcsout) pin. dcsout capture register 1 is present in the left data slot (as defined by the serial input format), and dcsout capture register 2 is present in the right data slot. the format for writing to the spi data capture setup registers is given in the spi section of this data sheet. dcsout lrclk bclk db level meters micro- controller AD1954 ext dacs 5.1 channel output figure 19. typical application of data capture feature
rev. 0 AD1954 ?8 table xx. data capture trap indexes and register select program count signal description index (9 bits) register select (2 bits) numeric format hpf out left 15 mult_out 1.23, clipped hpf out right 259 mult_out 1.23, clipped de-emphasis out left 19 mult_out 1.23, clipped de-emphasis out right 263 mult_out 1.23, clipped left biquad 0 output 34 mult_out 1.23, clipped left biquad 1 output 43 mult_out 1.23, clipped left biquad 2 output 52 mult_out 1.23, clipped left biquad 3 output 61 mult_out 1.23, clipped left biquad 4 output 70 mult_out 1.23, clipped left biquad 5 output 79 mult_out 1.23, clipped left biquad 6 output 88 mult_out 1.23, clipped right biquad 0 output 284 mult_out 1.23, clipped right biquad 1 output 293 mult_out 1.23, clipped right biquad 2 output 302 mult_out 1.23, clipped right biquad 3 output 311 mult_out 1.23, clipped right biquad 4 output 320 mult_out 1.23, clipped right biquad 5 output 329 mult_out 1.23, clipped right biquad 6 output 338 mult_out 1.23, clipped volume out left 114 mult_out 1.23, clipped volume out right 111 mult_out 1.23, clipped volume out sub 459 mult_out 1.23, clipped spatializer out left 115 mult_out 1.23, clipped spatializer out right 112 mult_out 1.23, clipped delay output left 190 mult_out 1.23, clipped delay output right 361 mult_out 1.23, clipped main compressor rms out (db) 154 db_out 24-bit positive binary, bit 19 corresponds to a 3 db change main compressor gain reduction 165 mci 2.22, 2 lsbs = 0 (linear) look-ahead delay output left 165 mdi 3.21, 2 lsbs truncated look-ahead delay output right 178 mdi 3.21, 2 lsbs truncated main compressor out left 175 mult_out 1.23, clipped main compressor out right 188 mult_out 1.23, clipped interpolator input left 191 mult_out 1.23, clipped (includes sub reinject) interpolator input right 362 mult_out 1.23, clipped (includes sub reinject) subchannel filter input 430 mult_out 1.23, clipped sub xover biquad 0 output 438 mult_out 1.23, clipped sub xover biquad 1 output 447 mult_out 1.23, clipped sub xover biquad 2 output 456 mult_out 1.23, clipped left xover biquad 0 output 99 mult_out 1.23, clipped left xover biquad 1 output 108 mult_out 1.23, clipped right xover biquad 0 output 349 mult_out 1.23, clipped right xover biquad 1 output 358 mult_out 1.23, clipped sub delay output 511 mult_out 1.23, clipped sub rms biquad output 467 mult_out 1.23, clipped sub rms output (db) 489 db_out 24-bit positive binary, bit 019 corresponds to a 3 db change sub compressor gain (linear) 495 mci 2.22, 2 lsbs = 0 sub channel output 511 mult_out 1.23, clipped
rev. 0 AD1954 ?9 serial data input port the AD1954? flexible serial data input port accepts data in two? complement, msb-first format. the left channel data field always precedes the right channel data field. the serial mode is set by using mode select bits in the spi control register. in all modes except for the right-justified mode, the serial port will accept an arbitrary number of bits up to a limit of 24 (extra bits will not cause an error, but they will be truncated inter- nally). in the right-justified mode, spi control register bits are used to set the word length to 16 bits, 20 bits, or 24 bits. the default on pow er-up is 24-bit mode. proper operation of the right-justified mode requires that there be exactly 64 bclks per audio frame. serial data input modes figure 20 shows the serial input modes. for the left-justified mode, lrclk is high for the left channel and low for the right channel. data is sam pled on the rising edge of bclk. the msb is left-justified to an lrclk transition, with no msb delay. the left-justified mode can accept any word length up to 24 bits. in i 2 s mode, lrclk is low for the left channel and high for the right channel. data is valid on the rising edge of bclk. the msb is left-justified to an lrclk transition but with a single bclk period delay. the i 2 s mode can be used to accept any number of bits up to 24. in right-justified mode, lrclk is high for the left channel and low for the right channel. data is sampled on the rising edge of bclk. the start of data is delayed from the lrclk edge by 16 bclk, 12 bclk, or 8 bclk intervals, depend- ing on the selected word length. the d efault word length is 24 bits; other word lengths are set by writ ing to bits 1 and 0 of control register 1. in right-justified mode, it is assumed that there are 64 bclks per frame. for the dsp serial port mode, lrclk must pulse high for at least one bit clock period before the msb of the left channel is valid, and lrclk must pulse high again for at least one bit clock period before the msb of the right channel is valid. data is sampled on the falling edge of bclk. the dsp serial port mode can be used with any word length up to 24 bits. in this mode, it is the responsibility of the dsp to ensure that the left data is transmitted with the first lrclk pulse and that synchronism is maintained from that point forward. right channel left channel lrclk bclk sdata lsb lsb lsb lsb lsb lsb lsb lsb left channel right channel lrclk bclk sdata lrclk bclk sdata lrclk bclk sdata 1/ f s dsp mode ?16 bits to 24 bits per channel notes 1. dsp mode doesn? identify channel. 2. lrclk normally operates at f s except dsp mode which is 2 f s . 3. bclk frequency is normally 64 lrclk but may be operated in burst mode. msb msb msb msb msb msb msb msb left-justified mode ?16 bits to 24 bits per channel i 2 s mode ?16 bits to 24 bits per channel right-justified mode ?select number of bits per channel figure 20. serial input modes
rev. 0 AD1954 ?0 digital control pins mute the AD1954 offers two methods of muting the analog output. by asserting the mute signal high, the left, right, and sub channel are muted. as an alternative, the user can assert the mute bit in the serial control register high. the AD1954 has been designed to minimize pops and clicks when muting and unmuting the device by automatically ramping the gain up or down. when the device is unmuted, the volume returns to the value set in the volume register. de-emphasis the AD1954 has a built-in de-emphasis filter that can be used to decode cds that have been encoded with the standard redbook 50 s/15 s emphasis response curve. this feature may be activated by the pin or by an spi write to the control register. when activat- ing with the pin, only the 44.1 khz sample-rate curve is available. when using the spi port, curves for 44.1 khz, 32 khz, and 48 khz are supported. analog output section figure 21 shows the block diagram of the analog output section. a series of current sources are controlled by a digital sigma-delta modulator. depending on the digital code from the modulator, each current source is connected to the summing junction of either a positive i-to-v converter or a negative i-to-v converter. two extra current sources that push instead of pull are added to set the midscale common-mode voltage. all current sources are derived from the vref input pin. the gain of the AD1954 is directly proportional to the magnitude of the current sources, and therefore the gain of the AD1954 is propor- tional to the voltage on the vref pin. with vref set to 2.25 v, the gain of the AD1954 is set to provide signal swings of 2 v rms differential (1 v rms from each pin). this is the recommended oper- ating condition. switched current sources out+ out i ref i ref ?dig_in i ref + dig_in vref in from digital sigma-delta modulator (dig_in) bias i ref figure 21. internal dac analog architecture when the AD1954 is used to drive an audio power amplifier and the compression feature is being used, the vref voltage should then be derived by dividing down the supply of the am- plifier. this sets a fixed relationship between the digital signal level (which is the only information available to the digital com- pressor) and the full-scale output of the amplifier (just prior to the onset of clipping). for example, if the amplifier power sup- ply drops by 10%, then the vref input to the amplifier will also drop by 10%, which will reduce the analog output signal swing by 10%. the compressor will therefore be effective in preventing clipping, regardless of any variation in amplifier supply voltage. since the vref input effectively multiplies the signal, care must be taken to ensure that no ac signals appear on this pin. this can be accomplished by using a large decoupling capacitor in the vref external resistive divider circuit. if the vref signal is derived by dividing the 5 v analog supply, then the time con- stant of the divider must effectively filter any noise on the supply. if the vref signal is derived from an unregulated power amplifier supply, then the time constant must be longer, since the ripple on the amplifier supply voltage will presumably be greater than in the case of the 5 v supply. the AD1954 should be used with an external third order filter on each output channel. the circuit shown in figure 22 combines a third order filter and a single-ended-to-differential converter in the same circuit. the values used in the main channel are for a 100 khz bessel filter, and those used in the subwoofer channel (figure 23) result in a 10 khz bessel filter. the lower frequency filter is used on the subwoofer output because there is no digital interpolation filter used in the subwoofer signal path. when calculating the resistor values for the filter, it is important to take into account the output resistance of the ad 1954, which is nominally 60 ? . for best distortion performance, 1% resistors should be used. the reason for this is that the single-ended performance of the AD1954 is about 80 db. the degree to which the single-ended distortion cancels in the final output is determined by the common-mode rejection of the external analog filter, which in turn depends on the tolerance of the components used in the filter. the sub output of the AD1954 has a lower drive strength than the left and right output pins ( 0.25 ma peak versus 0.5 ma peak for the left and right outputs). for this reason, it is best to use higher resistor values in the external sub filter. for best performance, a large (>10 f) capacitor should be connected between the filtcap pin and analog ground. this pin is connected to an internal node in the bias generator, and by adding an external capacitance to this pin, the thermal noise of the left/right channels is minimized. the sub channel is not affected by this connection.
rev. 0 AD1954 ?1 3.01k 3.7k 11k 56nf 1.5k 5.62k 5.62k 27nf 15nf 6.8nf 220nf 604 ?input + input out 560nf 270nf 6.8nf 150pf 2.2nf figure 22. recommended external analog filter for subchannel 1.50k 3.01k 2.80k 2.7nf npo 499 1.00k 806 1nf npo 820pf npo 270pf npo 2.2nf 549 ?input + input out figure 23. recommended external analog filter for main channels graphical custom programming tools custom programming tools are available for the AD1954 from adi. these graphical tools allow the user to modify the default signal processing flow by individually placing each block (e.g., biquad filter, phat stereo, dynamics processor) and connecting them in any desired fashion. the program then creates a file that is loaded into the AD1954? program ram. all of the contents of the parameter ram can also be set using these tools. for more information on these programming tools, con- tact sigmadsp@analog.com.
rev. 0 AD1954 ?2 appendix cookbook formulae for audio eq biquad coefficients (adapted from robert bristow-johnson? internet posting) for designing a parametric eq, follow the steps below. 1. given: frequency q db_gain s ample_rate 2. compute intermediate variables: a = 10^(db_gain/40) omega = 2 frequency/sample_rate sn = sin(omega) cs = cos(omega) alpha = sn/(2 q) 3. compute coefficients: b0 = ( 1 + a alpha)/( 1 + (alpha/a)) b1 = ? cs/( 1 + (alpha/a)) b2 = (1 ?(alpha a))/(1 + (alpha/a)) a1 = 2 cs/(1 + (alpha/a)) = ?1 a2 = ? 1 ?(alpha/a))/( 1 + (alpha/a)) 4. the transfer function implemented by the AD1954 is given by: h(z) = (b0 + b1 z ?1 + b2 z ?2)/(1 ?a1 z ?1 ?a2 z ?2) note the inversion in sign of a1 and a2 relative to the more standard form. this form is used in this document because the ad19 54 implements the difference equation using the formula below. y(n) = a1 y(n ?1) + a2 y(n ?2) + b0 x(n) + b1 x(n ?1) + b2 x(n ?2)
rev. 0 AD1954 ?3 outline dimensions 44-lead plastic quad flatpack [mqfp] (s-44) dimensions shown in millimeters 13.20 bsc sq 0.80 bsc 10.00 bsc sq 0.50 0.34 2.20 2.00 1.80 2.45 max 1.03 0.88 0.73 8 0.8 seating plane top view (pins down) 1 33 34 11 12 23 22 44 0.10 coplanarity compliant to jedec standards ms-022-ab 48-lead plastic quad flatpack [lqfp] (st-48) dimensions shown in millimeters top view (pins down) 1 12 13 25 24 36 37 48 0.27 0.22 0.17 0.50 bsc 7.00 bsc seating plane 1.60 max 0.75 0.60 0.45 view a 7 3.5 0 0.20 0.09 1.45 1.40 1.35 0.15 0.05 0.08 max coplanarity view a rotated 90 ccw pin 1 indicator 9.00 bsc compliant to jedec standards ms-026bbc seating plane
?4
?5
?6 c02760??/02(0) printed in u.s.a.

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